High-speed serial interfaces are increasingly being used as a back-plane interconnect between chips in communications, storage and enterprise, systems. High-speed serial interfaces incorporate serialization, deserialization and clock-data recovery functions and are generally refereed to as “SERDES” devices. To increase throughput and reduce the number of pins, a recent trend is to incorporate multiple SERDES ports in a single device. Power, area and performance are three key parameters that need to be optimized to achieve integration of multiple SERDES ports in a single device.
SERDES devices operate either as synchronous or plesiochronous systems. In synchronous systems, both the transmit and receive devices operate at the same exact clock frequency. Therefore, in synchronous systems no clock-rate compensation is required since both transmitting and receiving devices operate from the same exact reference clock frequency. In plesiochronous systems, transmit and receive devices each have their own separate local reference clocks which are close to each other in frequency, but have a very small offset in the order of ±100 ppm. An elastic-buffer is required to handle these small clock rate differences. Elastic-buffers insert/delete idles into the incoming data stream such that this data when retransmitted out does not cause overflow or underflow problems at the receiving device.
Clock Data Recovery is a technique for embedding clock and data into a single signal for the sake of transmission. High-speed serial data require the clocks to be embedded into the data stream to remove skew and jitter issues associated with transmitting this information separately from data. Jitter generally refers to a random variation in the timing of a signal, especially a clock. For clock jitter, there are two main parameters: period jitter and cycle to cycle jitter. Period jitter consists of peak to peak period jitter and root mean square (RMS) period jitter. The peak to peak period jitter is the difference between the maximum and minimum period of the clock signal. The RMS period jitter is the standard deviation of the peak to peak period jitter. Cycle to cycle jitter is the variation from one period to the next adjacent period of the signal. In order to determine the variation between adjacent periods, all consecutive periods need to be measured. The peak to peak period jitter is the worst case of cycle to cycle jitter.
Clock Data Recovery (CDR) is used on a receive-side to extract “incoming-clock” and data from a serial data stream. Serial data is first deserialized and then transferred to a “local-clock” domain with the use of elastic-buffers. Deserialized data can be transmitted out again with very low-jitter synchronous to local-clock. This operation is typically referred to as “retimer mode”. A “retimer” function attenuates all jitter at the input and outputs data with extremely low-jitter. However, the retimer function results in very high-latency due to elastic-buffers.
Fibre-Channel Arbitrated Loop (FCAL) is a fast serial bus interface standard intended to replace SCSI on high-end servers. Some applications, such as FCAL, require data regeneration to reduce or eliminate jitter due to channel inter-symbol interference (ISI). This requires that data be retransmitted synchronous to the incoming-clock. Incoming-clock is also referred as “recovered-clock”. The function of retransmitting data synchronous to the recovered-clock is termed as “repeater mode”. A “repeater” function does not require any elastic-buffers as there is no rate difference between incoming and outgoing data, but use is still made of CDR to extract incoming clock and data from a serial data stream. The repeater function results in very low-latency as no elastic-buffers are required.
Multi-port SERDES devices are usually implemented as either “retimer” or “repeater” devices, and ports are either all configured as repeater, or all configured as retimer. In these devices, an analog PLL (phase-locked loop) is typically used to perform the CDR function on each port. However, analog PLLs require a large area and consume more power than other port devices. These area and power limitations restrict the number of SERDES ports that can be integrated on a single device. Having all ports operate as either “repeater” or “retimer” limits the use of these devices.
In FCAL applications, disks are connected together using a simple loop topology. Data flows in a daisy-chain fashion from one disk to another. To prevent a single disk failure from making the loop non-operational, a port bypass circuit (PBC) is used. PBC provides a capability to bypass a non-working disk and still maintain a complete loop.
FIG. 1 illustrates an example of a port 10 in a PBC device as implemented in conventional products. Under typical conditions where all adjacent disks are operational, data from a first disk 12 is sent as RX data 14 to the input of a multiplexer, or mux, 16. Data is then output from the multiplexer 16 as TX data 18 to a second disk 20. In the case where the first disk 12 has failed, incoming data is received from the previous disk via input Bypass_IN 22 into the multiplexer 16. In the case where the second disk 20 has failed, the output from the multiplexer 16 is sent via the output Bypass_Out 24 to the next disk. The simple multiplexer 16 retransmits data with minimum latency in a synchronous manner. However, the simple mux does not attenuate any jitter introduced due to band-width limited channel from the disk to PBC since no retiming is performed. Moreover, at high data rates channel imperfections and ISI due to limited channel bandwidth degrade the signal integrity of the link significantly.
FIG. 2 shows a multiport SERDES device including PBC devices as implemented in conventional products using simple ports. In the situation of the multiport SERDES device 50 shown in FIG. 2, there are four operational disks indicated in bold outline, and five non-operational disks that are each bypassed, as indicated by the bypassed disks having a line through them. Most ports 52 implement a circuit as shown in FIG. 1 for enabling the bypass function. A path followed by data is indicated in bold lines, with the data bypassing the non-operational disks and proceeding to operational disks. CDR is typically implemented only on one port of the PBC 50 for jitter attenuation. Many known products use an analog PLL for CDR function. However, analog PLL-based CDRs are costly in terms of area, power and have limited frequency range. Therefore, due to power and area constrains, only few ports have CDRs with capability to attenuate incoming jitter and improve signal integrity.
As shown in FIG. 2, only the port with CDR has capability to attenuate jitter. Ports without CDR may not be able to meet input deterministic jitter (DJ) link-budget for the disk under worst-case bypass path since data is not retimed. Generally, CDR is placed at the input of the loop to attenuate jitter, as indicated by CDR 54 shown in bold lines. CDR can alternatively be placed at the output of the loop, as indicated by CDR 56 shown in dashed lines. In any case, CDR typically exists only at the transmit or receive end of the PBC, but not both. Since known devices have only a single CDR, this places a limitation on FCAL loop topology due to the need in FCAL to reduce or eliminate jitter.
In some recent approaches, a digital clock-recovery method has been used instead of the traditional analog PLL method described above. The basic idea in these more recent approaches is to use a single PLL to generate multiple clock-phases that are closely spaced together. It then uses a simple “phase-picking” algorithm to perform clock-data recovery. This approach is also referred to as digital-clock-data recovery (DCDR) since mostly digital logic is used to select an optimal clock-phase for clock-recovery. In DCDR a single PLL can be shared across multiple channels. Sharing a single-PLL across multiple channels results in very small area and power for the device, since this area and power can be amortized across multiple channels.
The use of DCDR can provide some relief to the area and power drawbacks of known approaches, which permits CDR to be implemented on more than one port in a SERDES device. However, each of these ports, while supporting bypass functionality, is still restricted to operation in either repeater or retimer mode. Therefore, if there are any changes with respect to a customer's needs with respect to system-jitter budget, latency and performance, these changing needs cannot be accommodated by the existing solutions, which are aimed at optimizing some of those performance characteristics, to the detriment of the other characteristics.
It is therefore desirable to provide a port that is configurable to provide bypass, repeater and retimer functions, and where multiple such ports can be provided in a SERDES device, or port bypass circuit.